Integration of an Operating System/PUS Software and an SoC-FPGA Board

Cyclone-V SoC-FPGA-Board
Cyclone-V Hardware in protective acrylic housing

Integration of a customized Linux distribution an specially configured kernel on an FPGA/System-on-Chip device in the frame of a research project of the Bundeswehr University Munich.

The Cyclone 5-SoC-FPGA that combines an ARM Cortex-A9 Dual-Core HPS (Hard Processor System) with an FPGA has been selected as hardware platform. This device was chosen because of its high performance and configurability and it has been deployed on the OPS-SAT satellite.

The system is used for the simulation of FDIR algorithms (Fault Detection, Isolation, Recovery) that are controlled via a PUS TM/TC interface.

PUS (Packet Utilization Standard) is an ESA-Standard (ECSS-E-70-41A), that defines the telemetry and telecommand communication in space flight.


Integration of an Operating System/PUS Software and an SoC-FPGA Board

Cyclone-V SoC-FPGA-Board
Cyclone-V Hardware in protective acrylic housing

A similar project has been undertaken for the company TTTech Computertechnik AG in fall 2014. A different hardware board with the same Cyclone 5 System-on-Chip device has been selected.